Analog to digital conversion is often performed using an algorithmic analog to digital converter (ADC). Algorithmic ADC's generally require a minimum of circuitry. The present invention is particularly concerned with ADC's useful in conjunction with focal plane arrays for detecting infrared radiation. Such focal planes are used in spacecraft, which operates in very cold (10K) environments. Each focal plane array includes a large number of individual detectors. The output of each detector generally must be converted to a digital signal for processing. Therefore, a large number of ADC's are required, dictating that the ADC's occupy minimal space and consume minimal power.
An example of current algorithmic analog to digital converters is illustrated in FIG. 1. An analog signal is received on the signal input line or system input terminal 11. The analog input signal is sampled in sample and hold circuitry 13. A switch 15 connects the output terminal of the sample and hold circuit to an input terminal of a comparator 17 and to the positive input terminal of a subtractor 19.
The input analog signal is assumed to have a maximum value of Vm. The comparator 17 compares the input signal sample with a threshold voltage Vm/2. If the signal exceeds the threshold voltage, the comparator outputs a binary bit one (1).
A switch control 21 connected to the output of the comparator controls the value or voltage applied to the negative input terminal of the subtractor 19. The subtractor removes from the input analog signal a voltage or value corresponding to the threshold exceeded.
The switch control applies the appropriate voltage to the negative input terminal of the subtractor. If the comparator outputs a one, indicating that the threshold Vm/2 has been exceeded, the switch control applies the voltage Vm/2 to the negative input terminal of the subtractor. If the comparator outputs a zero, indicating that the threshold Vm/2 has not been exceeded, the switch control applies zero voltage to the negative input terminal of the subtractor, so that the output of the subtractor has the same amplitude as the input.
Thus, the most significant bit of the digital representation of the magnitude of the analog signal received on the system input terminal has been generated on the comparator output terminal.
The next most significant bit is generated by multiplying the output of the subtractor 19 by two in a multiplier 23, and repeating the above comparison step.
The switch 15 closes the connection between a sample and hold circuit 25 connected to the output terminal of the multiplier and the input of the comparator 17. The doubled output of the subtractor can then be compared with the threshold voltage Vm/2. The output of the comparator 17 (a binary one if the threshold voltage is exceeded, a binary zero if the threshold voltage is not exceeded}is the second most significant bit. The switch control 21 applies either the voltage Vm/2 or zero voltage to the negative input of the subtractor 19, so that the subtractor subtracts that voltage from the doubled previous subtractor output.
The third most significant bit is generated by repeating the above process, as is the fourth most significant bit.
The successive bits generated may be applied to an accumulator comprising a number of delay elements such as flip-flops 27, 28, and 29. Using the accumulator shown, a four-bit digital representation of the analog signal value received can be generated by accumulating the three bits in the delay elements, and then allowing the bits to be read out of the third flip-flop 29 in the order of most significant bit to least significant bit.
Each bit decision requires that the comparator 17 accurately determine whether the sample is above or below the threshold to within one-half the value of the least significant bit. As is known to those skilled in the art, the greater the accuracy of the comparator, the greater the time required for the comparator to settle and generate an output. Thus, while accomplishing the purpose of generating a digital representation of an input analog signal with a minimum of circuitry, the algorithmic analog to digital converter illustrated in FIG. 1 has its maximum conversion speed limited by the time necessary for the comparator to settle to one-half of the least significant bit, for each bit decision.